This review paper deals with performance analysis of the published works for circuit level realization of radix-4 Booth Encoder/decoders. Starting from general concept of Booth algorithm in brief form, the conventional truth table is discussed. Subsequently, the modifications which led to the circuit level implementations along with the complete and comparative analysis for the selected works, is provided. Simulations using HSPICE for TSMC 0. 18μ m CMOS technology and 1. 8V power supply have been performed for comparing these works. Considering the required optimizations applied to the mentioned works, it can be deduced that 1. 5 XOR gate level delay is reachable for radix-4 Booth encoding scheme while the output waveforms are free of any glitches. The optimized version of Booth Encoder has been embedded in a 16x16 bit parallel multiplier in which, the measured latency after post layout simulations is 1992ps; which demonstrates the high potential of chosen radix-4 Booth encoding scheme for utilization in high speed parallel multipliers.

This review paper contains the discussion about performance analysis of high speed 4-2 compressor architectures, starting from the general idea; conventional form for implementation of this building block along with its truth table has been studied. Thereafter, the modified versions which show promise for high speed multiplier implementations along with their benefits and drawbacks were demonstrated and comprehensively analyzed. Following the same principles, an optimized structure for the 4-2 compressor is obtained which has 2 XOR gate level delay for the critical path and contains the least delay among the reported works. As another advantage, because of uniform paths the output waveforms will be free of any glitches. Simulation results for TSMC 0. 18 μ m CMOS technology and 1. 8V power supply using HSPICE have been provided to show the superiority of our designed architecture in terms of the speed performance. Finally, to confirm the correct behavior of proposed compressor, an 8x8 bit multiplier was designed which can operate at the frequency of 500MHz without employing any special multiplication algorithm for partial product generation.

BACKGROUND AND OBJECTIVES: The study provides an assessment of fuel wastage, particulate matter particles pollution, and noise pollution at three toll Booths near district Varanasi, India. The objective of the study is to analyze the effects of vehicle idling conditions on road tolls in terms of pollution and fuel wastage. METHODS: The study used mathematical formulation on queuing observations for assessment of fuel wastage due to vehicle idling at toll Booths. Handheld device HT-9600 Air Particle counter was used for getting the readings of PM2. 5 and PM10. SL10 noise meter of Extech Instruments was used for measuring the noise levels at the selected three toll Booths of Dafi Toll Booth, Lalanagar Toll Booth, and Mohania Toll Booth. FINDINGS: The study assessed a greater extent of fuel wastage at all the three toll Booths with maximum fuel wastage at Dafi Toll Booth due to vehicle idling. In terms of air pollution, severe levels of particulate matter particles were observed over all the three toll Booths. The noise levels over the three toll Booths were also observed significantly high. CONCLUSION: The study suggested that serious measures are required to control and regulate toll Booths to avoid vehicle idling, which will lead to savings of fuel and air and noise pollution.

This paper presents a high-speed, low-power and low area Encoder for implementation of flash ADCs. Key technique for design of this Encoder is performed by convert the conventional 1-of-N thermometer code to 2-of-M codes (M = ¾ N). The proposed Encoder is composed from two-stage; in the first stage, thermometer code are converted to 2-of-M codes by used 2-input AND and 4-input compound AND-OR gates. In the second stage by two ROM Encoders, 2-of-M codes determine n-1 MSB bits and one LSB bit. The advantages of the proposed Encoder rather than other similar works are high speed, low power consumption, low active area, and low latency with same bubble error removing capability. To demonstrate the mention specifications, 5-bit flash ADCs with conventional and proposed Encoders in their Encoder blocks, are simulated at 2-GS/s and 3. 5-GS/s sampling rates in 0. 18-μ m CMOS process. Simulation results show that the ENOB of flash ADCs with conventional and proposed Encoders are equal. In this case, the proposed Encoder outputs are determined almost 30-ps faster rather than the conventional Encoder at 2-GS/s. Also, the power consumptions of the conventional and proposed Encoders were 17. 94-mW and 11. 74-mW at 3. 5-GS/s sampling rate from a 1. 8-V supply, respectively. Corresponding, latencies of the conventional and proposed Encoders were 3 and 2 clock cycles. In this case, number of TSPC D-FFs and logic gates of the proposed Encoder is decreased almost 39% compared to the conventional Encoder.

Nowadays, the use of hardware/software codesign has grown dramatically in the design of embedded systems since it can improve the processing power, system efficiency, and the total cost of production. In this method, some parts of the system are implemented in hardware and the other parts are implemented in software in order to satisfy the system constraints, including power consumption, area and processing time. This paper proposes a parallel architecture for motion estimation in HEVC Encoder. In the proposed method, the motion estimation part of the Encoder, which has a high computational complexity, is implemented in hardware, and the computational complexity of this part is improved using parallel processing. The hardware implementation of motion estimation part is much less complex than the adopted HM reference software, making it more suitable for embedded systems. Experimental results show a significant improvement over software implementation.

In this paper, we introduce the subclass $\mathcal{K}\mathcal{S}(\alpha)$ of univalent functions in $\mathcal{A}$ and study some properties of this class. We apply matters of differential subordinations, to investigate some results concerning the subclasses $\mathcal{K}\mathcal{S}(\alpha)$ and $\mathcal{B}\mathcal{S}(\alpha)$ of $\mathcal{A}$, where $\alpha \in [0,1)$.

Web Application Firewall (WAF) is known as one of the Intrusion Detection System (IDS) solutions for protecting web servers from HTTP attacks. WAF is a tool to identify and prevent many types of attacks, such as XSS and SQL-injection. In this paper, deep machine learning algorithms are used for enriching the WAF based on the anomaly detection method. Firstly, we construct attributes from HTTP data, to do so we consider two models namely n-gram and one-hot. Then, according to Auto-Encoder LSTM (AE-LSTM) as an unsupervised deep leaning method, we should extract informative features and then reduce them. Finally, we use ensemble isolation forest to train only normal data for the classifier. We apply the proposed model on CSIC 2010 and ECML/ PKDD 2007 datasets. The results show AE-LSTM has higher performance in terms of accuracy and generalization compared with naï ve methods on CSIC dataset; the proposed method also have acceptable detection rate on ECML/PKDD dataset using n-gram model.